> > The use of the term "delayed" is kind of a misnomer, at least when compared to
> > delayed branches.
> Not really, any changes to the program counter are delayed for one instruction.
> > My guess is that Tekken2's
> > use truely is a bug where a register was inadvertantly used in the first cycle
> I believe it was a missing nop in the jr ra of the called function, so it was
> executing the first instruction of the next function ( IIRC it was a mfc2 ). The
> instruction at ra then uses the register & needs it to be the old value, the
> pipeline should stall but it doesn't. In theory you should count the stalled
> cycles, but then you should also count the cache misses too. AFAIK the real
> r3000 doesn't have a stalling circuit, but the derivative the PSX uses does.
> I don't think the pipelines can be advanced when a cache misses or you'd end up
> with pretty random behaviour with regards to whether instructions in the delay
> slot would be executed or not.
I think the big problem was that it is a COP2 instruction, which makes things much more interesting than any memory or register access. In this case it relies on the exact implementation of the COP2 engine.
I wonder, did Tekken2 work correctly on the PS2 in PS1 emulation mode ? The R3K CPU is the same, but I thought the COP2 engine was emulated, so I wonder if they had to hack Tekken2 .. :)