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SubjectRe: CPU emulation questions.. Reply to this message
Posted byR. Belmont
Posted on04/22/04 09:30 AM

> The code blocks wont ever exactly "align" correctly with interrupts though will
> they? I guess it's a speed/accuracy tradeoff..

Yeah. That's generally why dynarecs are only done for later RISC CPUs, where code can't reliably depend on the cycle timing. Of course, you can impose an artifical maximum block length if accuracy's your thing, but you'll in turn lose speed.

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Subject  Posted byPosted On
*CPU emulation questions..  cabaret voltaire04/21/04 08:44 AM
.*Re: CPU emulation questions..  galibert04/21/04 09:41 PM
..*Re: CPU emulation questions..  cabaret voltaire04/22/04 04:06 AM
....Re: CPU emulation questions..  R. Belmont04/22/04 09:30 AM